ARCHIVES

1. Muhammad Raza Naqvi, “Low power network on chip architectures: A survey”, Computer Science and Information Technologies, Vol. 2,
No. 3, November 2021, pp. 158~168.
2. Ahmed Ben Achballah , Slim Ben Othman and Slim Ben Saoud, “Problems and challenges of emerging technology networks −on −chip:
A review”, Microprocessors and Microsystems 53 (2017) 1–20.
3. K. Paramasivam, “Network On-Chip and Its Research Challenges”, ICTACT Journal on Microelectronics, July 2015, Volume: 01, Issue:
02 83-87.
4. Fardin Mohammadi Darvandi , Mohammad Trik , Danial Hodaraji and Kumarth Nazari , “ A study on Low-power challenges in NOC”,
IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 2 Issue 8, July 2015.
5. Mark Buckler, Wayne Burleson and Greg Sadowski, “Low-power Networks-On-Chip: Progress and Remaining Challenges”, Symposium
on Low Power Electronics and Design,132-134,2013.
6. Fensch, C. et al., "Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors” IEEE Tr. Computers, 2013.
7. Wen-Chung Tsai, Ying-Cherng Lan, Yu-Hen Hu and Sao-Jie Chen, “Review Article ON Networks on Chips: Structure and Design
Methodologies”, Journal of Electrical and Computer Engineering,Volume 2012, 15 pages.
8. Viswanathan N, K. Paramasivam and K. Somasundaram, “Exploring Optimal Topology and Routing Algorithm for 3D Network on Chip”,
American Journal of Applied Sciences 9 (3): 300-308, 2012.